New

Analog IC Design Senior Principal Engineer

Marvell Semiconductor, Inc.
paid time off, flex time, 401(k)
United States, California, Santa Clara
5488 Marvell Lane (Show on map)
Jan 11, 2025
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Central Engineering AMS-IP team provides leading-edge SerDes and Chiplet IO PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. What You Can Expect Seeking a Senior Principal Analog IC Designer to be part of a Marvell's central engineering team designing highly sophisticated CMOS transceiver/SERDES/PLL products. Responsibilities would span architectural investigations and implementation for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets and performing design verification using industry standard tools such as SPICE, Spectre, MATLAB etc. In this role, successful candidate will lead a team of analog design engineers, interface with layout, verification, and application teams and manage delivery of analog IP to successfully bring designs from concept to production. What We're Looking For MS/PhD in Electrical Engineering with 15+ years of related professional experience. A successful candidate should have experience in some of the following designs: PLL, Data Converters, Oscillators and high-speed SerDes design including Receiver and Transmitter design. Experience in Single-ended High Density Parallel Interface for Chip to Chip Communication, DDR5/LPDDR5; GDDR6/LPDDR6 a plus Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must Knowledge of the fundamentals on signal integrity improvement, noise reduction and Multi-GHz low-jitter clock generation & distribution. Good understanding of analog layouts in FinFet and its effect on high-speed designs Experienced in system level pre-tape out analog validation Experienced in lab chip bring-up and debugging efforts Strong communication skills Expected Base Pay Range (USD) 168,210 - 252,000, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. #LI-TD1