Staff Physical Design Engineer

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

In this pivotal role, you will contribute to the development of advanced backend design flows and methodologies. Your expertise in block-level PNR and hands-on experience in physical design tools will help us achieve high-performance, low-power, and reliable designs across a spectrum of challenging SoC products. You'll also have the opportunity to shape backend design strategies and be instrumental in Marvell's success in delivering industry-leading data infrastructure solutions.

What You Can Expect

• Comprehensive Block-Level PNR Responsibilities:
  • Take charge of block-level PNR tasks, from floor planning and power grid design to place and route, clock tree synthesis, and timing closure.
  • Perform power and signal integrity analysis to ensure optimal design reliability and robustness.
• Collaborative Physical Design Process:
  • Partner with frontend, integration, and verification teams to ensure alignment and continuity throughout the SoC design lifecycle.
  • Ensure physical verification compliance, including DRC/LVS and antenna checks, to achieve first-pass silicon success.
• Methodology Development and Process Automation:
  • Develop and refine physical design methodologies, applying automation through scripting to streamline design workflows.
  • Support the creation of design flows and processes that improve efficiency, consistency, and scalability across Marvell's physical design teams.

What We're Looking For

• Education & Experience:
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 3+ years of experience in physical design with a focus on block-level PNR for advanced CMOS process nodes (e.g., 7nm, 5nm, or below).
• Technical Proficiency:
  • Proficient with industry-standard EDA tools for physical design, including Cadence Genus and Innovus, and Synopsys IC Compiler and Fusion Compiler.
  • Strong expertise in static timing analysis tools such as Tempus or PrimeTime and EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail.
  • Working knowledge of physical verification and formal verification tools (e.g., Calibre, LEC, Formality) is advantageous.
• Programming & Automation Skills:
  • Demonstrated ability to create scripts (Tcl, Perl, Makefile) for automating design processes and improving overall workflow efficiency.
• Key Attributes:
  • Detail-oriented, self-motivated team player with effective communication skills and a commitment to collaborative success. environment

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.